This invention relates to a semiconductor device and a method for fabricating same, and in particular to a semiconductor device, in which at least a lateral trench is formed in the interior of a single-crystal semiconductor substrate having a principal surface, which trench is filled with a substance other than the singlecrystal semiconductor, and a method for fabricating the same.
Heretofore it is well known to form an n.sup.+ or P.sup.+ conductivity type buried layer in the interior of a singlecrystal semiconductor substrate having a principal surface (JP-A-56-1556), to form a capacitance by burying an insulating material therein (ISSCC 84/FRIDAY, Feb. 24, 1984/CONTINENTAL 5-9/11:45 A.M.) by a buried an insulator for taking-out an electrode (JP-A-59-161867, JP-A-61-237471), etc. For forming such various sorts of buried layers, heretofore, the epitaxial technique and a high energy ion implantation technique have been widely utilized. However all these techniques have had several problems.
At first consider a bipolar transistor having an n.sup.+ conductivity type buried layer disclosed in JP-A-56-1556. FIG. 42 shows the construction of this transistor. In the figure reference numeral 1 is a p conductivity type Si substrate; 7 is an isolation insulating layer; 8 is a deep trench isolation insulating layer; 9 is a trench filling Si layer; 10 is a base taking-out electrode; 153 is an n.sup.+ conductivity type diffusion layer for taking-out an n.sup.+ conductivity type buried layer 152; 141 is a surface protecting insulating layer; 16 is an emitter taking-out electrode; 18 is a base electrode; 19 is an emitter electrode; and 20 is a collector electrode. That is, the epitaxial layer 200 is formed on a collector region consisting of an n.sup.+ conductivity type diffusion layer 152 and that an intrinsic base region 13, an n.sup.+ conductivity type emitter region 17, etc. are constructed within the epitaxial layer 200.
The buried layer may be formed also by the method, by which high energy ions are implanted in the Si substrate.
By the method described above the epitaxial layer 152 is unnecessary and the base region 13 and the emitter region 17 are formed after the formation of the n+ conductivity type buried layer.
In the bipolar transistor fabricated by the prior art techniques described above it is required that the n.sup.+ conductivity type buried diffusion layer 152 used as the collector has a low resistance for increasing the operation speed of the transistor and an abrupt impurity concentration distribution. In particular, for the n.sup.+ conductivity type buried diffusion layer 152 antimony (Sb) has been used as diffused impurities in order to prevent impurity outward diffusion in the step of forming the epitaxial layer 200 on the n.sup.+ conductivity type buried diffusion layer 152 or variations in the impurity distribution in a succeeding step for high temperature heat treatment. However since the solid solubility of Sb into Si is as low as 3-5.times.10.sup.19 cm.sup.-3, even the sheet resistance of an n.sup.+ conductivity type buried diffusion layer 1.5 .mu.m thick is essentially as high as 30 .OMEGA./.quadrature.. Therefore it was difficult to reduce the collector resistance.
Further, during the growth of the epitaxial layer 200 on the n.sup.+ conductivity type buried diffusion layer 152 constructed selectively, positional deviations from the buried diffusion layer pattern due to the dependence of the epitaxial growth speed on the crystal-lographical surface orientation are unavoidable. This caused a hindrance to the reduction of the size and the increase in the degree of integration of elements. Further there was another problem that it was difficult to deal with a large quantity of products in a conventional epitaxial growth apparatus, which raised the production cost.
On the contrary, by the method, by which the n.sup.+ conductivity type buried layer 152 is formed by high energy ion implantation, all the problems described above concerning the formation of the epitaxial layer 200 are solved. However, it is known that by the high energy ion implantation implanted ions are not distributed symmetrically with respect to the maximum concentration range, but the distribution has a long tail from the position of the maximum concentration towards the surface of the semiconductor substrate. Therefore there remained a problem that no abrupt impurity distribution could be Obtained. Furthermore, the high energy ion implantation method has still another problem that crystal defects are produced during the formation of a high impurity concentration buried layer and that it is difficult to restore the crystallographical property even by a succeeding heat treatment step. Therefore by this method no excellent junction characteristics could be obtained.
Still another problem of the prior art techniques concerning the n.sup.+ conductivity type buried diffusion layer 152 consists in that the occupation area required for the taking-out of the collector and the wiring is large, which causes a hindrance to the reduction of the size and the increase in the degree of integration of elements. Furthermore still another problem concerning the increase in the degree of integration consists in that a sufficiently great interval or an element isolating region having a sufficiently great depth is required for isolating adjacent n.sup.+ conductivity type buried diffusion layers.
Another problem of the prior art techniques concerns a memory device whose constituent elements are transistors having a prior art structure. That is, in a prior art semiconductor memory device, although the n.sup.+ conductivity type buried diffusion layer 152 has been used as a region for storing information, a measure should be taken in the circuit for preventing destruction of stored information due to a large number of electrons produced by .alpha. ray irradiation within the semiconductor substrate 1, so-called soft error misoperation. This has caused a serious problem against the decrease in the storage charge density of the memory device.
An object of this invention is to provide a bipolar transistor including a buried impurity layer having a low resistivity and an abrupt impurity distribution, for which production of crystal misoperation is not feared and which can solve the problems of the prior art techniques, by means of which a transistor of a superfine and super high integration is possible and which transistor is thus not expensive.
Another object of this transistor is to provide a bipolar transistor memory, in which no .alpha.-ray soft errors are produced.
Next the DRAM (Dynamic Random Access Memory) disclosed in ISSCC 84/FRIDAY, Feb. 24, 1984/CONTINENTAL 5-9/11:45 A.M.) will be considered. FIG. 43A is a cross-sectional view illustrating the construction of this DRAM and FIG. 43B indicates an equivalent circuit thereof, in which reference numeral 1100 is a p.sup.+ conductivity type semiconductor substrate; 1030 is a p.sup.- conductivity type epitaxial layer; 1031 is a field oxide layers 1032 and 1321 are n.sup.+ conductivity type drain diffusion layers, which are bit lines formed in the direction perpendicular to the sheet of the figure; 1033 and 1331 are capacitor oxide layers; and 1034 is a polycrystalline Si storage electrode serving as an electrode of a capacitor element constituted between that p.sup.+ conductivity type semiconductor element and itself. Further 1035 and 1351 are n.sup.+ conductivity type buried source diffusion layers and 1036 and 1361 are gate oxide layers of vertical type MOS switching transistors; and 1037 indicates word lines made of polycrystalline Si serving as gate electrodes of switching transistors A and B. In the DRAM cell indicated in FIG. 43A, a transistor and a capacitor element are buried at each intersection of every word line and every bit line. Consequently, contrarily to the fact that the reduction of the size of the memory cell having a usual structure is based on the reduction of the size of the processing, the memory cell indicated in FIG. 43B is characterized in that the area of a cell can be significantly reduced with respect to the cell having a usual structure in spite of a same design rule.
Although the prior art techniques are efficient for the remarkable reduction of the size of each cell, no attention is paid to mutual interference between adjacent cells. Therefore, they have had a problem that the integration is hindered. That is, in the construction indicated in FIG. 43A, in which adjacent cells are close to each other, current paths are produced between the n.sup.+ conductivity type drain diffusion layers 1032 and 1321 or the n.sup.+ conductivity type buried source diffusion layers 1035 and 1351 in the switching transistor portion, which has given rise to a problem that erroneous operations take place. This problem of the production of current paths is more serious between buried sources.
Furthermore, the prior art techniques have had a problem that the resistance against erroneous operations due to the .alpha. ray irradiation, so-called soft error misoperation, in not sufficient. Pairs of electron and hole are generated within the semiconductor substrate by the .alpha.-ray irradiation and electrons are diffused towards the surface of the structure. However, in the structure indicated in FIG. 43A, polycrystalline Si storage electrodes 1034 and 1341, which are charge storage regions, are enclosed by oxide layers 1033 and 1331 and no soft error misoperation are produced in these parts. Further the semiconductor substrate is also of P.sup.+ conductivity type, the life time of electrons is short, and the resistance against soft error is better than that of the usual construction. However, since electrons diffused to the neighborhood of the surface of the substrate are trapped by the buried source diffusion layer 1035 or 1351, the problem of the erroneous operations due to soft errors is not solved even by the memory cell having the structure as indicated in FIG. 43A.
Another problem of the structure described above concerns the formation of the p.sup.- conductivity type epitaxial layer on the p.sup.+ conductivity type semiconductor substrate. That is the P conductivity type high impurity concentration substrate is formed usually by using boron (B) as added impurity. However, since the diffusion coefficient of B is great, there is a problem that redistribution of impurity is produced easily by high temperature heat treatment, which is unavoidable in the fabrication process. Consequently this has given rise to problems that the breakdown voltage of the buried source diffusion layers 1035 and 1351 is lowered by the redistribution of B to the p.sup.- conductivity type epitaxial layer 1030, that the threshold voltage of switching transistors is raised, etc. Another problem of the prior art structure described above consists in that the word line 1037 and the storage electrodes 1034 and 1341 are adjacent to each other only through the thin oxide films 1036 and 1361. That is, the potential of the storage electrode is apt to be interfered by the word line signal, which gives rise easily to a problem of write-in thereof, etc.
An object of this invention is to provide a DRAM cell, which can remove the disadvantages of the memory cell having the prior art structure; in which no problems such as interference between cells, interference between word lines, .alpha.-ray soft error, etc. are produced; for which redistribution of p.sup.+ conductivity type impurities is not feared; and by means of which a superfine and a high density integration are possible.
Next a buried insulating layer for taking-out an electrode disclosed in JP-A-59-161867 is indicated in FIG. 44, in which reference numeral 2001 is a p conductivity type Si singlecrystal substrate, whose principal surface is (100) plane; 2100 is lateral type pnp transistor; 2101 is a vertical type npn transistor; 2002 is an n.sup.+ conductivity type buried layer; 2061 a buried insulating layer made of SiO.sub.2 ; 2008, 2009 and 2010 are p.sup.+ conductivity type diffusion layers, which are the emitter region and the collector region of the lateral type pnp transistor 2100 and the graft base region of the vertical type npn transistor 2101, respectively; 2011 is a p conductivity type diffusion layer region, which is the intrinsic base region of the vertical type npn transistor 2101; 2012 and 2015 are the n.sup.+ conductivity type emitter region and the n.sup.+ conductivity type collector region, respectively, of the vertical type pnp transistor 2101; 2071 is an emitter taking-out electrode of the lateral type pnp transistor 2100 made of polycrystalline Si; 2007 is the collector taking-out electrode of the lateral type pnp transistor 2100, serving also as the base taking-out electrode of the vertical type npn transistors 2101; 2013 is the emitter taking-out electrode of the vertical type npn transistor 2101; 2014 is an insulating layer; 2016, 2017, 2018 and 2019 are the emitter electrode and the collector electrode of the lateral type pnp transistor 2100 and the emitter electrode and the collector electrode of the vertical type npn transistor 2101, respectively, made of metal layers, whose principal component is A1. The collector electrode 2017 of the lateral type pnp transistor 2100 serves also as the base electrode of the vertical type npn transistor 2101.
In a known bipolar transistor having the structure as indicated in FIG. 44, all the base-collector junction outside of the active region of the vertical type npn transistor 2101, and the base-collector and the base-emitter junctions of the lateral type pnp transistor 2100 are replaced by thick insulating layers 2061 so that the parasitic capacitance is significantly reduced. Furthermore, since the graft base 2010 constituted by a p.sup.+ conductivity type diffusion layer is formed also on a buried insulating layer 2061, the shortest path between the n.sup.+ conductivity type buried layer 2002 serving as a collector and the base is increased and the base-collector breakdown voltage is improved. Consequently the transistor having the structure indicated in FIG. 44 has advantages to have a high breakdown voltage and to achieve a high speed operation.
In such a bipolar transistor a thick buried insulating layer 2061 has been formed 1 by selective oxidation of the bottom portion of a trench formed by etching the semiconductor substrate 1 in the direction perpendicular to the principal surface thereof by sputter ion etching, 2 by selective oxidation of a surface obtained by etching isotropically the bottom of the trench, and 3 by making a water-drop-shaped single-crystal region amorphous by implanting ions selectively in the bottom portion of the trench and by selectively oxidizing a surface obtained by selectively removing this amorphous region. By either one of the methods 1 to 3 it is not possible to extend satisfactorily the buried insulating layer 2061 in the lateral direction so as to be positioned below the graft base 2010 and none of them is used in practice. By the method indicated by 1, since the extension of the graft base 2010 formed by using the base taking-out electrode 2007 as a diffusion source due to heat treatment, etc. in the fabrication process is much faster than the oxide film growth of the buried insulating layer 2061, it is almost impossible to construct the buried insulating layer 2061 below the graft base 2010 by the present technique. In the case where it is formed by the method indicated by 2, if the amount of the isotropic etching is increased, it is possible to extend satisfactorily the region of the formation of the buried insulating layer 2061 in the lateral direction. However, since the tunnel making is advanced also in the vertical direction, the n.sup.+ conductivity type buried layer 2002 is corroded wastefully. Therefore this has given rise to a problem of undesirably increasing the collector resistance and at the same time hindering the reduction of the size. By the method indicated by 3, by which the buried insulating layer 2061 is extended in the lateral direction within the singlecrystal substrate 2001, the degree of the extension in the lateral direction is determined unequivocally by the conditions of the ion implantation on the basis of characteristics of the lateral extension of the amorphous layer by the ion implantation. However, in order to realize a lateral extension of desired size and, in particular, a lateral extension above several 100 nm, it is indispensable to use a high current ion implantation apparatus having a high acceleration energy from several 100 keV to several MeV. Therefore this method has had a drawback that semiconductor devices could not be fabricated in a simple manner with a low cost. Further secondary misoperation due to high energy and high current ion implantation are produced within the singlecrystal substrate 2001, from which the amorphous layer is selectively removed, which has been apt to give rise to a problem to worsen electric characteristics such as increase in leak current, etc.
An object of this invention is to realize a semiconductor device comprising a protruding semiconductor region formed in a surface region of a semiconductor substrate; buried insulating layers formed at least on both the side of the bottom of the protruding semiconductor region on the surface of the semiconductor substrate; a taking-out (lead-out) electrode layer, which is in contact with a side wall of the protruding semiconductor region and which is formed on the buried insulating layer; and a region doped with impurity, which is formed on the side wall portion in the protruding semiconductor region in contact with the taking-out electrode layer, in which the end portion of the buried insulating layer formed at the bottom portion of the side wall in the protruding semiconductor region extends satisfactorily towards the central portion of the protruding semiconductor region.
Further, speaking more concretely concerning the bipolar transistor, the object of this invention is to provide a superfine and super high speed bipolar transistor having a buried insulating layer separating the graft base from the high impurity concentration buried collector diffusion layer to a desired extent in the lateral direction in a desired region without impairing the reduction of the size, which can be fabricated with a high controllability by a simple fabrication process.
Next the buried insulating layer for taking-out an electrode disclosed in JP-A-61-237471 is indicated in FIG. 45, in which reference numeral 2001 is a p conductivity type Si singlecrystal substrate, for which a (100) plane is usually used as the principal surface from the point of view of reducing surface energy levels; 2200 is an isolation insulating layer separating elements, 2030 is a gate insulating layer; 2040 is a gate electrode; 2050 is a gate protecting insulating layer; 2080 is a gate side wall insulating layer; 2091 is a source taking-out (lead-out) electrode; 2092 is a drain taking-out (lead-out) electrode; 2710 is a buried insulating layer; 2110 and 2111 are a source diffusion layer and a drain diffusion layer, respectively; and 2130 and 2140 are a source electrode and a drain electrode, respectively. Since in an MOS transistor having the prior art structure indicated in FIG. 45, the buried insulating layer 2710 can be constructed so that it is sufficiently thick, the transistor is characterized in that the parasitic capacitance component can be satisfactorily reduced with respect to that in an MOS transistor having a usual structure and therefore the operation speed is increased.
In such an MOS transistor, the buried insulating layer 2710 has been fabricated by selective oxidation of the etching region on the Si substrate 2001, on which the gate electrode 2040 serving as a mask was formed. Consequently the transistor was not so constructed that the buried insulating layer was extended to the side wall portion of the source-drain junction in the Si substrate region below the gate electrode 2040 and thus it was impossible to realize such a structure.
The structure of the buried insulating layer 2710 will be evaluated by the numerical analyzing method from the point of view of the improvement of the performance, and in particular the increase of the breakdown voltage and the high current density of a superfine MOS transistor and obtained results will be explained. That is, in the structure, in which the buried insulating layer 2710 is formed at the bottom portion of the source-drain junction such as in the prior art structure, although the effect to reduce the parasitic capacitance can be obtained, the effect to alleviate the drain high electric field is not obtained at all. Consequently, in an MOS transistor having an extremely short channel the prior art structure is not at all efficient with respect to the improvement of the effect because of a strong electric field on the drain side, i.e. the so-called short channel effect and the phenomenon of the lowering of the punchthrough voltage. From the point of view of the short channel effect and the increase of the punchthrough voltage it is desirable to form a thick insulating layer at the side portion of the drain junction so as to absorb the drain strong electric field.
According to the prior art technique indicated in FIG. 45, a method for burying an insulating layer by the thermal oxidation method or the deposition method at a region, where the side surface of the drain junction is to be formed, after having selectively removed the region by etching using a fluoric acid and nitric acid mixed solution, microwave etching, etc., is also conceivable. However, by the method described above, since the etching proceeds isotropically and there is a problem in its controllability, it is feared that essential disadvantages take place that the semiconductor substrate portion corresponding to the channel region is also etched, that the portion is made to be insulating, etc. and therefore this method is not practical.
Another object of this invention is to construct a thick insulating layer with a good controllability related to the self-alignment with the gate electrode at the side surface portion of the drain junction in the semiconductor substrate right below the gate electrode by the same structure as described for the bipolar transistor.